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Tests

Semiconductor Reliability Standards include tests for electrostatic discharge (ESD), radiation-hardness, longevity and life-span estimations through accelerated testing, as well as other varied tests for semiconductors and semiconductor devices.

IEC 62137-4 Ed. 1.0 b:2014

Electronics assembly technology - Part 4: Endurance test methods for solder joint of area array type package surface mount devices

IEC 62137-4:2014 specifies the test method for the solder joints of area array type packages mounted on the printed wiring board to evaluate solder joint durability against thermo-mechanical stress. This part of IEC 62137 applies to the surface mounting semiconductor devices with area array type packages (FBGA, BGA, FLGA and LGA) including peripheral termination type packages (SON and QFN) that are intended to be used in industrial and consumer electrical or electronic equipment. IEC 62137-4 includes the following significant technical changes with respect to IEC 62137:2004: - test conditions for use of lead-free solder are included; - test conditions for lead-free solders are added; - accelerations of the temperature cycling test for solder joints are added.

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ASTM F615M-95(2013)

Standard Practice for Determining Safe Current Pulse-Operating Regions for Metallization on Semiconductor Components (Metric)

1.1 This practice covers procedures for determining operating regions that are safe from metallization burnout induced by current pulses of less than 1-s duration. Note 1 In this practice, metallization refers to metallic layers on semiconductor components such as interconnect patterns on integrated circuits. The principles of the practice may, however, be extended to nearly any current-carrying path. The term burnout refers to either fusing or vaporization. 1.2 This practice is based on the application of unipolar rectangular current test pulses. An extrapolation technique is specified for mapping safe operating regions in the pulse-amplitude versus pulse-duration plane. A procedure is provided in Appendix X2 to relate safe operating regions established from rectangular pulse data to safe operating regions for arbitrary pulse shapes. 1.3 This practice is not intended to apply to metallization damage mechanisms other than fusing or vaporization induced by current pulses and, in particular, is not intended to apply to long-term mechanisms, such as metal migration. 1.4 This practice is not intended to determine the nature of any defect causing failure. 1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

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ASTM F1894-98(2011)

Test Method for Quantifying Tungsten Silicide Semiconductor Process Films for Composition and Thickness

1.1 This test method covers the quantitative determination of tungsten and silicon concentrations in tungsten/silicon (WSi x ) semiconductor process films using Rutherford Backscattering Spectrometry (RBS). ( 1 ) This test method also covers the detection and quantification of impurities in the mass range from phosphorus + (31 atomic mass units (amu) to antimony (122 amu). 1.2 This test method can be used for tungsten silicide films prepared by any deposition or annealing processes, or both. The film must be a uniform film with an areal coverage greater than the incident ion beam ( 2.5 mm). 1.3 This test method accurately measures the following film properties: silicon/tungsten ratio and variations with depth, tungsten depth profile throughout film, WSi x film thickness, argon concentrations (if present), presence of oxide on surface of WSi x films, and transition metal impurities to detection limits of 1 10 14 atoms/cm 2 . 1.4 This test method can detect absolute differences in silicon and tungsten concentrations of 3 and 1 atomic percent, respectively, measured from different samples in separate analyses. Relative variations in the tungsten concentration in depth can be detected to 0.2 atomic percent with a depth resolution of 70 + . 1.5 This test method supports and assists in qualifying WSi x films by electrical resistivity techniques. 1.6 This test method can be performed for WSi x films deposited on conducting or insulating substrates. 1.7 This test method is useful for WSi x films between 20 and 400 nm with an areal coverage of greater than 1 by 1 mm 2 . 1.8 This test method is non-destructive to the film to the extent of sputtering. 1.9 A statistical process control (SPC) of WSi x films has been monitored since 1993 with reproducibility to 4 %. 1.10 This test method produces accurate film thicknesses by modeling the film density of the WSi x film as WSi 2 (hexagonal) plus excess elemental Si 2 . The measured film thickness is a lower limit to the actual film thickness with an accuracy less than 10 % compared to SEM cross-section measurements (see 13.4). 1.11 This test method can be used to analyze films on whole wafers up to 300 mm without breaking the wafers. The sites that can be analyzed may be restricted to concentric rings near the wafer edges for 200-mm and 300-mm wafers, depending on system capabilities. 1.12 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard. 1.13 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. The reader is referenced to Section 8 of this test method for references to some of the regulatory, radiation, and safety considerations involved with accelerator operation.

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ASTM E493/E493M-11(2017)

Standard Practice for Leaks Using the Mass Spectrometer Leak Detector in the Inside-Out Testing Mode

1.1 This practice 2 covers procedures for testing devices that are sealed prior to testing, such as semiconductors, hermetically enclosed relays, pyrotechnic devices, etc., for leakage through the walls of the enclosure. They may be used with various degrees of sensitivity (depending on the internal volume, the strength of the enclosure, the time available for preparation of test, and on the sorption characteristics of the enclosure material for helium). In general practice the sensitivity limits are from 10 10 to 10 6 Pa m 3 /s (10 9 standard cm 3 /s to 10 5 standard cm 3 /s at 0 C) for helium, although these limits may be exceeded by several decades in either direction in some circumstances. 1.2 Two test methods are described:... 1.3 Units The values stated in either SI or std-cc/sec units are to be regarded separately as standard. The values stated in each system may not be exact equivalents: therefore, each system shall be used independently of the other. Combining values from the two systems may result in non-conformance with the standard. 1.4 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. 1.5 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.

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IEC 62483 Ed. 1.0 b:2013

Environmental acceptance requirements for tin whisker susceptibility of tin and tin alloy surface finishes on semiconductor devices

IEC 62483:2013 describes the methodology applicable for environmental acceptance testing of tin-based surface finishes and mitigation practices for tin whiskers on semiconductor devices. This methodology may not be sufficient for applications with special requirements, (i.e. military, aerospace, etc.). Additional requirements may be specified in the appropriate requirements (procurement) documentation. This first edition is based on JEDEC documents JESD201A and JESD22-A121A and replaces IEC/PAS 62483, published in 2006. This first edition constitutes a technical revision. This edition includes the following significant technical changes with respect to the previous edition: a) The content of IEC/PAS 62483 was added to the content of JESD201A as Annex A. b) A methodology was introduced for environmental acceptance testing of tin-based surface finishes and mitigation practices for tin whiskers. c) A Clause 6 was introduced detailing the reporting requirements of test results.

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IEC 62417 Ed. 1.0 b:2010

Semiconductor devices - Mobile ion tests for metal-oxide semiconductor field effect transistors (MOSFETs)

"IEC 62417:2010 provides a wafer level test procedure to determine the amount of positive mobile charge in oxide layers in metal-oxide semiconductor field effect transistors. It is applicable to both active and parasitic field effect transistors. The mobile charge can cause degradation of microelectronic devices, e.g. by shifting the threshold voltage of MOSFETs or by inversion of the base in bipolar transistors."

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IEC 62373 Ed. 1.0 b:2006

Bias-temperature stability test for metal-oxide, semiconductor, field-effect transistors (MOSFET)

Provides a test procedure for a bias-temperature (BT) stability test of metal-oxide semiconductor, field-effect transistors (MOSFET)

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ASTM F76-08(2016)e1

Standard Test Methods for Measuring Resistivity and Hall Coefficient and Determining Hall Mobility in Single-Crystal Semiconductors

1.1 These test methods cover two procedures for measuring the resistivity and Hall coefficient of single-crystal semiconductor specimens. These test methods differ most substantially in their test specimen requirements. 1.2 These test methods do not provide procedures for shaping, cleaning, or contacting specimens; however, a procedure for verifying contact quality is given. Note 1: Practice F418 covers the preparation of gallium arsenide phosphide specimens. 1.3 The method in Practice F418 does not provide an interpretation of the results in terms of basic semiconductor properties (for example, majority and minority carrier mobilities and densities). Some general guidance, applicable to certain semiconductors and temperature ranges, is provided in the Appendix. For the most part, however, the interpretation is left to the user. 1.4 Interlaboratory tests of these test methods (Section 19 ) have been conducted only over a limited range of resistivities and for the semiconductors, germanium, silicon, and gallium arsenide. However, the method is applicable to other semiconductors provided suitable specimen preparation and contacting procedures are known. The resistivity range over which the method is applicable is limited by the test specimen geometry and instrumentation sensitivity. 1.5 The values stated in acceptable metric units are to be regarded as the standard. The values given in parentheses are for information only. (See also 3.1.4 .) 1.6 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. 1.7 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.

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IEEE C62.35-2010

Standard Test Methods for Avalanche Junction Semiconductor Surge-Protective Device Components

Avalanche breakdown diodes used for surge protection in systems with voltages equal to or less than 1000 V rms or 1200 V dc are discussed in this standard. The avalanche breakdown diode surge suppressor is a semiconductor diode which can operate in either the forward or reverse direction of its V-I characteristic. This component is a single package, which may be assembled from any combination of series and/or parallel diode chips.

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SAE AIR 1921-1985 (SAE AIR1921-1985)

Spark Igniter Semiconductor Resistance Measurement Using Controlled Energy Levels ( Reaffirmed: Jun 1994 )

The purpose of this report is to provide specific information on instrumentation and procedures to measure spark igniter tip semiconductor resistance at an applied voltage level of 500 to 1000 volts without introducing heating effects. This report describes a method of semiconductor resistance measurement using controlled energy levels and a digital processing oscilloscope to acquire and process test data.

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SAE J 1879-2014 (SAE J1879-2014)

Handbook for Robustness Validation of Semiconductor Devices in Automotive Applications

This document will primarily address intrinsic reliability of electronic components for use in automotive electronics. Where practical, methods of extrinsic reliability detection and prevention will also be addressed. The current handbook primarily focuses on integrated circuit subjects, but can easily be adapted for use in discrete or passive device qualification with the generation of a list of failure mechanisms relevant to those components. Semiconductor device qualification is the main scope of the current handbook. Other procedures addressing extrinsic defects are particularly mentioned in the monitoring chapter. Striving for the target of Zero Defects in component manufacturing and product use it is strongly recommended to apply this handbook. If it gets adopted as a standard, the term “shall” will represent a binding requirement. This document does not relieve the supplier of the responsibility to assure that a product meets the complete set of its requirements.

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ASTM F2113-01(2011)

Standard Guide for Analysis and Reporting the Impurity Content and Grade of High Purity Metallic Sputtering Targets for Electronic Thin Film Applications

1.1 This guide covers sputtering targets used as thin film source material in fabricating semiconductor electronic devices. It should be used to develop target specifications for specific materials and should be referenced therein. 1.2 This standard sets purity grade levels, analytical methods and impurity content reporting method and format. 1.2.1 The grade designation is a measure of total metallic impurity content. The grade designation does not necessarily indicate suitability for a particular application because factors other than total metallic impurity may influence performance.

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SAE SSB 1/002-2014 (SAE SSB1/002-2014)

Environmental Tests and Associated Failure Mechanisms

This document is an annex to EIA Engineering Bulletin SSB-1. Guidelines for Using Plastic Encapsulated Microcircuits and Semiconductors in Military, Aerospace and Other Rugged Applications. This document provides reference information concerning the environmental stresses associated with tests specifically designed to apply to (or have unique implications for) plastic encapsulated microcircuits and semiconductors, and the specific failures induced by these environmental stresses.

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SAE SSB 1/004A-2009 (SAE SSB1/004A-2009)

Failure Rate Estimating

This document is an annex to EIA Engineering Bulletin SSB-1, Guidelines for Using Plastic Encapsulated Microcircuits and Semiconductors in Military, Aerospace and Other Rugged Applications (the latest revision). Failure-Mechanism-Driven Reliability Monitoring draws upon the concepts and implementation of line controls, process stability, and effective monitoring programs in lieu of qualifying a product based solely on a fixed list of tests. A supplier must identify those failure mechanisms that may be actuated through a given product / process change(s), and must design and implement reliability tests adequate to assess the impact of those failure mechanisms on system level reliability. In order for this to be effective, the supplier establishes a thorough understanding of and linkage to their reliability monitoring program. Statistical Reliability Monitoring (SRM) is a statistically based methodology for monitoring and improving reliability; it involves identification and classification of failure mechanisms, development and use of monitors, and investigation of failure kinetics allowing prediction of failure rate at use conditions. Failure kinetics are the characteristics of failure for a given physical failure mechanism, including (where applicable) acceleration factor, derating curve, activation energy, median life, standard deviation, characteristic life, instantaneous failure rate, etc. The failure rate of semiconductor devices is inherently low. As a result, the semiconductor industry uses a technique called accelerated testing to assess device reliability. Elevated stresses are used to produce the same failure mechanisms as would be observed under normal use conditions, but in a shorter time period. Acceleration factors are used by device manufacturers to estimate failure rates based on the results of accelerated testing. The objective of this testing is to identify these failure mechanisms and eliminate them as a cause of failure during the useful life of the product. This document provides reference information concerning methods commonly used by the semiconductor industry to estimate failure rates from accelerated test results. These methods are frequently used by OEMs in conjunction with physics of failure reliability analysis to assess the suitability of plastic encapsulated microcircuits and semiconductors for specific end use applications.

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