Historical
IPC J-STD-003C+Amd1-2014
Solderability Tests for Printed Boards
J-STD-003C prescribes test methods, defect definitions and illustrations for assessing the solderability of printed board surface conductors, attachment lands, and plated-through holes utilizing either tin-lead or lead-free solders. This standard is intended for use by both vendor and user. The objective of the solderability test methods described in this standard is to determine the ability of printed board surface conductors, attachment lands, and plated-through holes to wet easily with solder and to withstand the rigors of the printed board assembly processes. This standard describes test methods by which both the surface conductors (and attachment lands) and plated-through holes may be evaluated for solderability. Revision "C" contains the latest information about GR&R (gauge reproducibility & repeatability) of the solderability tests as well as updated illustrations. Amendment 1 corrects editorial errors as well as adds clarifying statements to many areas of the document.
Association Connecting Electronics Industries [ipc]