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ESD Association Standard Practice for Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits - Transient Latch-up Testing - Device Level

This document defines procedures to characterize the latch-up sensitivity of integrated circuits triggered by fast transients

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ESD Association Standard Practice for Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits - Transient Latch-up Testing - Device Level

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ESD Association Standard Practice for Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits - Transient Latch-up Testing - Device Level

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